In this specific technical field, it is well known that in an information storage unit (FIG. 2) the controller functions to provide an interface for the user, according to a predetermined convention, by using an interface and some services made available by the memory.
This is the typical condition of storage systems like disk-on-chip, memory card or smart card, as schematized in the here-attached FIG. 2.
In a general control unit (FIG. 3) a predetermined software level attends to providing interface functions to overhanging software levels by using said interface and services made available by the memory.
In an ideal system, without errors, the memory receives/sends the data sent/required by the controller without error possibility.
In a real system, however, it is almost impossible to send and store data without errors.
Data-storage flash memories use the most developed technologies to integrate the most information per area unit. For these applications NAND, Multilevel NAND and Multilevel NOR memories are commonly used. Error probability of these memories increases as the memory ages because of well-known physical phenomena.
For example, in a floating gate memory cell, the information storage capacity is influenced by several mechanisms, such as: the ability to maintain charge, the “read disturb” mechanism, the “program disturb” mechanism, the SILC phenomenon, each having a different influence as the memory ages.
In substance, the error tolerance which must be offered by the memory system is determined by the kind of application required by the user and it is usually lower than the error tolerance offered by flash memories during their life span.
A convenient memory system must provide some devices and functions to show externally, or at overhanging levels, an error tolerance being lower or equal to the one required by the application. This is commonly achieved by using error correction techniques.
These error correction techniques provide that the information is split in words of K bits and that these words are conveniently coded with N bits, where R redundancy bits are added to the K information bits. Only at this point are words written in the memory.
During the information reading, the K original information bits are decoded from the N bits read by the memory.
The presence of R redundancy bits allows the original information to be recovered if the error number is lower than W. Different codings for the K information bit protection from W errors by coding on N bits are known in the prior art.
For convenience of illustration, a practical case of a linear and systematic coding (144, 128) for correcting two errors (N=144 bits, K=128 bits, W=2 bits) will be considered hereinafter.
With reference to FIG. 6, the coding and decoding of such a code can be summarised as follows:
The vector “c” to be stored, composed of 144 bits, is obtained as a vector product of “i”, a 128-bit data vector, with the binary generating matrix “G” composed of 128 rows by 144 columns. In the particular linear and systematic coding case G is composed of an identity matrix I and a parity matrix P. The vector “c” being obtained thus comprises the repetition of the data vector “i” and the parity vector is obtained as vector product iP. Formally expressed:c=i·G=i·[I,P]=[i, iP]
The matrix P is a binary matrix of size 128×16 being conveniently chosen (a method for obtaining this matrix is known in the art).
For the decoding step a so-called syndrome “s” must be calculated:s=r·HT=p⊕+d·PwhereG·HT=0
The syndrome “s”, a 16-bit vector, is obtained as a vector product between the vector “r”, a data vector of 144 bits read by the memory and composed of a 128-bit data part “d” and a 16-bit parity part “p”, and the transpose of the matrix H. It can be shown that the syndrome is equivalent to the sum in GF(2) of the parity vector “p” with the vector product of the vector d with the parity matrix P.
The syndrome s is void if the data vector “r” is correct; while, according to the way the matrix P is defined, “s” has a sole value for each possible configuration of one or two errors affecting “r”.
To achieve this coding and decoding scheme some solutions are known, which are schematically shown in FIGS. 4a and b. 
In the first solution of FIG. 4a a general memory is used. This memory stores data “i” and parity bits “iP”, calculated by the controller. The coding and decoding task for correcting errors is entrusted to the controller.
The disadvantages of this solution are:                high latency time between the data request and the availability thereof.        
In fact standard flash memories use a limited-size interface bus to communicate with the controller. Although the memory internal reading is commonly performed for pages having several bits (for example 144 bits), the communication towards the controller is bound to a word sequence on the data bus. Since for calculating the syndrome, and thus for detecting and correcting the error, all the page bits are necessary, data are available for the user only after transferring all K bits of the page (data+parity) in the controller and after calculating the parity.                a memory overhead in the controller.In fact the K bits of the page (data+parity) must be loaded in the controller memory with subsequent occupation of a controller memory area.        an overhead in the controller processing resources.        
In fact the controller must, for each data page, read all K bits of the page (data+parity). For each page it must therefore calculate the parity and, if the latter indicates an error, activate the correction.
For performing these operations the controller requires a calculation power overhead so as not to influence the memory system overall performances; moreover a part of the transmission band between the memory and the controller is used for transmitting parity bits being not strictly necessary for the user application.
In this second prior art solution, shown in FIG. 4b, the coding and decoding task is entrusted to the memory. The syndrome decoding for correcting two errors is generally too onerous in terms of area to be advantageously implemented in the memory.
The technical problem underlying an embodiment of the present invention is to provide an integrated memory system, having such structural and functional characteristics as to ensure an automatic error correction in data storage overcoming the drawbacks mentioned with reference to the prior art.